So, a glimmer of progress in the saga that is my final year project!

( progress! )

It works, with a 'testing' XOR core. The bottom dump is the key xor the second dump. Yay! That's running in FPGA via pcie.
The project is, looking at my original Gantt chart, around three weeks behind schedule, mainly because I had a bit of a nightmare (well, a lot of a nightmare) grappling with the Xilinx PCI-Express core. Once I got it running - about a week ago - everything else was fairly straightforward. I'm hoping I can make up for lost time over Christmas (which should be do-able, because I built so much 'spare time' in to my schedule, anticipating this kind of catastrophe) and get everything done on time.

Also troubling me is that all my Uni stuff this semester is due on the same day, and there's some impressive juggling going on between my VR group project (to model a chunk of the Univeristy in Second Life) and another module, in which I am required to model some stuff in a formal Finite-State language.

Most of the VR stuff is done now. My part of the project is to interface the 3D environment to the Uni's web-based 'learning environment', Blackboard. Blackboard, however, doesn't kick out any nice webservices, so there's a lot of screen-scraping and generally horrible code going on in there. All of that's now done, though, so I just need to finish it off by writing some scripts in Second Life to make everything feel immersive. Watch this space.

Well, I appear to have 'dodged a bullet' with my Final Year Project - when I actually started work on the project, I discovered it was pretty much impossible to do what I wanted to do, in the way I wanted to do it.

While I was aiming to 'hide' my extra encryption/decryption logic in the extra CAS latency cycle gained by using CL2 RAM in an CL3 system, I overlooked the fact that cas latency timings are used only during data writes, and not during reads, as their intention is to allow an error-free comparison of charges in memory to reference values. There's a timing parameter which specifies a minimum time after a write, but that doesn't seem to be widely supported. Because of this, and some other issues (mainly relating to wanting to run 'proper' strong encryption instead of just a simple xor scheme) I had to look in to other approaches.

My 'backup plan' of using 'registered' memory, at the expense of mainstream motherboard compatibility, was rapidly shot down as I realised that only control lines - not the data/address buses - are registered in such a scheme.

I hastily fabricated a new plan - to attatch an FPGA in between the CPU and motherboard of the system, and did a few days research and all-out panic-driven studying. I finally concluded that this was also a bad idea, as it relies heavily on work in areas I'm not confident in (such as high-speed PCB design) and I was eventually forced to drop the whole project idea - two days before I was due to hand in a 'project plan' document detailing the project, and containing a detailed plan of how I was going to perform it.

I did, however, somehow manage to think of a new project, and build this plan. I'm not entirely sure how I achieved this (besides the obvious 'I didn't actually sleep').

The new project is a study in to the ease of design, speed, and power usage of an FPGA-based hardware implimentation of various encryption algorithms. Put simply, I'm going to develop FPGA cores for six or so crypto schemes, benchmark them all in as many different areas as I can (including in a fairly 'real-world' application), in as reproducible a way as possible, and then write a nice report about it.

It's a lot less star-spangled, I think, but it should be orders of magnitude easier than the previous proposition. I don't need to do any of the stuff that I'm really inexperienced at - ie, PCB design - which would normally be a bad thing, but the previous project disaster has really brought home how much I need to be careful not to overstretch myself, and keep the project as do-able as possible. Having said that, there are a few things in there that I haven't done before, which should prove challenging. I've got around 30 weeks to do it, and since I've planned my time really generously, I'm hoping I'll get a couple of weeks spare to 'enhance' the project with extra algorithms, or benchmarks on different hardware.

Wish me luck!